1. Field of the Invention
This invention relates to a semiconductor integrated circuit, specifically to a technology for structuring a circuit to improve characteristics of the circuit by giving regularity to a hierarchical structure of interconnections in a hierarchical design having multi-layer interconnections.
2. Description of the Related Art
A prior art semiconductor integrated circuit structure will be explained referring to FIGS. 6A and 6B hereinafter. The explanation will be given by taking a differential amplifier, which is frequently used in bipolar linear integrated circuits, as an example.
In the basic structure of the differential amplifier 11, both emitters of a first transistor Q11 and a second transistor Q12 are connected to a constant current transistor Q13, and each of the collectors of the transistors Q11 and Q12 is connected to a power supply Vcc through load resistors R11 and R12, respectively, as shown in FIG. 6A.
Compensating variable factors of the transistors to suppress their effects on an output is made possible by increasing the difference between signals Vin1 and Vin2, which are respectively applied to bases of the transistors Q11 and Q12, the bases serving as input terminals, and creating output signals Vout1 and Vout2 from collectors of the transistors Q11 and Q12, respectively.
Attention is paid to secure pair matching of the transistors Q11 and Q12 as well as pair matching of the load resistors R1 and R12, since a midpoint potential of the output would shift, resulting in a loss of desired circuit characteristics, if balance between elements is lost. Here, pair matching means uniformity in the characteristics of the elements forming the pair.
However, even though attention is paid to secure the pair matching of the transistors Q11 and Q12 as well as pair matching of the load resistors R11 and R12 in the above mentioned circuit, there are problems, which are described below, when the circuit is laid out to dispose each of the semiconductor elements according to a circuit diagram, for instance from left to right (or from right to left).
That is, each of the emitter follower circuits 42 and 43 connected to each of the pair of the differential outputs of the differential amplifier 11 is disposed to one side (right side) of a center line of the differential amplifier 11, as shown in FIG. 6A. The emitter follower circuit 42 includes a transistor Q14, a constant current transistor Q16 and an emitter resistor R13 of the constant current transistor Q16. The emitter follower circuit 43 includes a transistor Q15, a constant current transistor Q17 and an emitter resistor R14 of the constant current transistor Q17.
Therefore, pair matching of the semiconductor integrated circuit which includes the differential amplifier 11 could be lost, and an impedance offset could arise when the circuit blocks are interconnected, resulting in deterioration in the circuit characteristics.
Furthermore, interconnections 12 and 14 need to be formed with a layer which is different from the layer used for interconnections 13 and 15 (the interconnections 13 and 15 are formed with the first layer interconnection while the interconnections 12 and 14 are formed with the second layer interconnection in the above configuration), since the interconnection 12, inputting the output from the collector of the transistor Q11 to a base of the transistor Q14 of the emitter follower circuit 42, intersects with the interconnection 13 connecting the resistor R12 and the collector of the transistor Q12. Similarly, the interconnection 14, inputting the output from the collector of the transistor Q12 to a base of the transistor Q15 of the emitter follower circuit 43 intersects with the interconnection 15 connecting the emitter of the transistor Q14 and the collector of the transistor Q16 of the emitter follower 42, as shown in FIG. 6B, because both the emitter followers 42 and 43 connected with the outputs of the differential amplifier 11 are disposed to one side (right side) of a center of the differential amplifier 11 as described above. High frequency characteristics are deteriorated due to signal cross talk when the interconnections intersect with each other. In addition, pair matching is lost because the length of the interconnection 12 differs from that of the interconnection 14. Therefore, when the circuit blocks are interconnected, desired characteristics might not be obtained because of the offset due to the impedance.
In the integrated circuit of the prior art, because rules (purpose of usage and pair matching) have not been established for each layer of the interconnections, each of interconnections are formed with a different layer taking the easy way out when the intersection of the interconnections is expected, thus causing deterioration in the circuit characteristics.
Furthermore, for design automation of a semiconductor integrated circuit with a hierarchical structure, for example, when interconnecting within each circuit block as well as between the circuit blocks, a layout method of the semiconductor integrated circuit such as using the first layer metal for horizontal interconnection and using the second layer metal for vertical interconnection has been proposed.
However, when the interconnection is made based on the criteria mentioned above (such as using the first layer metal for horizontal interconnection and using the second layer metal for vertical interconnection), a plurality of interconnection layers is used even where a single layer of interconnection could make the interconnection, making the interconnection too complicated.